MIPS Pipeline Processor
Implemented a five-stage MIPS pipeline processor in Vivado using Verilog and FPGA, capable of calculating and showing results on 7-Segment displays.
Tools:
- Vivado
- Verilog
- FPGA
Implemented a five-stage MIPS pipeline processor in Vivado using Verilog and FPGA, capable of calculating and showing results on 7-Segment displays.
Tools: